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NXP Semiconductors /MIMXRT1011 /SPDIF /SRPC

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Interpret as SRPC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GainSel_0)GainSel 0 (LOCK)LOCK 0 (ClkSrc_Sel_0)ClkSrc_Sel

ClkSrc_Sel=ClkSrc_Sel_0, GainSel=GainSel_0

Description

PhaseConfig Register

Fields

GainSel

Gain selection:

0 (GainSel_0): 24*(2**10)

1 (GainSel_1): 16*(2**10)

2 (GainSel_2): 12*(2**10)

3 (GainSel_3): 8*(2**10)

4 (GainSel_4): 6*(2**10)

5 (GainSel_5): 4*(2**10)

6 (GainSel_6): 3*(2**10)
LOCK

LOCK bit to show that the internal DPLL is locked, read only
ClkSrc_Sel

Clock source selection, all other settings not shown are reserved:

0 (ClkSrc_Sel_0): if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)

1 (ClkSrc_Sel_1): if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)

3 (ClkSrc_Sel_3): if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK

5 (ClkSrc_Sel_5): REF_CLK_32K (XTALOSC)

6 (ClkSrc_Sel_6): tx_clk (SPDIF0_CLK_ROOT)

8 (ClkSrc_Sel_8): SPDIF_EXT_CLK

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data